DocumentCode :
2412043
Title :
Evaluation on the reliable operation of a Gate-Level Pipelined Self Synchronous system against PVT and aging
Author :
Devlin, Benjamin ; Ikeda, Makoto ; Asada, Kunihiro
Author_Institution :
Dept. of Electron. Eng., Univ. of Tokyo, Tokyo, Japan
fYear :
2010
fDate :
17-21 Oct. 2010
Firstpage :
110
Lastpage :
113
Abstract :
The reliable operation against PVT (process, voltage, and temperature) variation and aging effects has been measured of a Gate-Level Pipelined Self Synchronous FPGA (SSFPGA) design in 65nm CMOS. The SSFPGA employs a 38×38 array of 4-input, 3-stage Self Synchronous Configurable Logic blocks. Throughput has been measured at 2.97GHz at 1.2V, with correct operation from 750mV to 1.6V at 25°C. The operation with errors being inserted into the SSFPGA was compared to a conventional synchronous FPGA, which showed the SSFPGA had 4.2 times error free operation. The effect of aging was also measured on the SSFPGA using accelerated cycle between 0°C and 120°C at 2V, which showed the SSFPGA has 8% longer correct operation before chip malfunction past a 10% delay margin commonly used in synchronous systems..
Keywords :
ageing; field programmable gate arrays; integrated circuit reliability; logic testing; accelerated cycle; aging effects; chip malfunction; delay margin; frequency 2.97 GHz; gate-level pipelined self synchronous FPGA; process-voltage-temperature variation; self synchronous configurable logic blocks; temperature 0 degC to 120 degC; voltage 1.2 V; voltage 2 V; voltage 750 mV to 1.6 mV; Aging; Delay; Field programmable gate arrays; Frequency measurement; Noise; Semiconductor device measurement; Throughput;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Integrated Reliability Workshop Final Report (IRW), 2010 IEEE International
Conference_Location :
Stanford Sierra, CA
ISSN :
1930-8841
Print_ISBN :
978-1-4244-8521-5
Type :
conf
DOI :
10.1109/IIRW.2010.5706500
Filename :
5706500
Link To Document :
بازگشت