DocumentCode :
2412179
Title :
A new approach to test generation and test compaction for scan circuits
Author :
Pomeranz, Irith ; Reddy, Sudhakar M.
Author_Institution :
Sch. of Electr. & Comput. Eng., Purdue Univ., Lafayette, LA, USA
fYear :
2003
fDate :
2003
Firstpage :
1000
Lastpage :
1005
Abstract :
We propose a new approach to test generation and test compaction for scan circuits that eliminates the distinction between scan operations and application of primary input vectors. Under this approach, the scan-in, scan-select and scan-out lines are treated as conventional primary inputs or primary outputs of the circuit. As a result, limited scan operations, where scan chains are shifted a number of times smaller than their lengths, are incorporated naturally into the test sequences generated by this approach. This leads to very aggressive compaction, resulting in test sequences with the lowest known test application times for benchmark circuits.
Keywords :
automatic test pattern generation; flip-flops; integrated circuit testing; integrated logic circuits; sequential circuits; limited scan operations; scan circuits; test application times; test compaction; test generation; test sequences; Application software; Benchmark testing; Circuit faults; Circuit testing; Cities and towns; Clocks; Compaction; Fault detection; Flip-flops; Logic testing;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Design, Automation and Test in Europe Conference and Exhibition, 2003
ISSN :
1530-1591
Print_ISBN :
0-7695-1870-2
Type :
conf
DOI :
10.1109/DATE.2003.1253735
Filename :
1253735
Link To Document :
بازگشت