DocumentCode :
2412261
Title :
3D simulation of charge collection and SEU of 0.13µm partially depleted SOI SRAM
Author :
Zhang, Xiaochen ; Yue, Suge ; Wang, Liang ; Li, Jiancheng
Author_Institution :
Beijing Microelectron. Technol. Inst., Beijing, China
fYear :
2010
fDate :
17-21 Oct. 2010
Firstpage :
149
Lastpage :
152
Abstract :
In this paper, the charge collection and parasitic bipolar effect of SOI NMOS devices in case of different ion strike locations have been analyzed through 3D simulation. The simulation results show that the strike at drain region can cause charge collection comparable with the collection induced by strike at the gate region above body. Single event upset (SEU) simulations of SRAM cell have been conducted. Results indicate that the reverse-biased drain region is sensitive to SEU, as well as the gate region. The largest amount of charge collection in device and the lowest LET threshold of SEU in SRAM both occur when the ion strikes at the drain/body junction area and passes through the centre part of the reverse junction.
Keywords :
SRAM chips; integrated circuit modelling; silicon-on-insulator; 3D simulation; SOI SRAM; charge collection; parasitic bipolar effect; partially depleted; single event upset; size 0.13 mum; Electric potential; Junctions; Logic gates; Random access memory; Silicon; Silicon on insulator technology; Single event upset;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Integrated Reliability Workshop Final Report (IRW), 2010 IEEE International
Conference_Location :
Stanford Sierra, CA
ISSN :
1930-8841
Print_ISBN :
978-1-4244-8521-5
Type :
conf
DOI :
10.1109/IIRW.2010.5706511
Filename :
5706511
Link To Document :
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