DocumentCode :
2412288
Title :
A High-Performance 8-Tap FIR Filter Using Logarithmic Number System
Author :
Sun, Yan ; Kim, Min Sik
Author_Institution :
Sch. of Electr. Eng. & Comput. Sci., Washington State Univ., Pullman, WA, USA
fYear :
2011
fDate :
5-9 June 2011
Firstpage :
1
Lastpage :
5
Abstract :
This paper presents an approach for implementing a 8-tap high-performance digital FIR (Finite Impulse Response) filter using Logarithmic Number System(LNS). In the past, FIR filters were implemented by conventional number system; therefore, the speed was limited due to the multiply accumulate operations. We realize a fast FIR filter by utilizing the Logarithmic Number System, which allows simple implementation of multiplication using a fixed-point adder. And the serious demerit of Logarithmic Number System´s algorithm, conversions to and from the conventional number representations is effectively overcome by utilizing our pipeline architecture, so the delay and complexity of the filter is reduced. The critical path was reduced from a multiply-accumulate operation to an adder operation, and our FIR filter can operate at 1.3G Hz under the condition of 1.2 V power supply using SMIC 0.13um CMOS technology, and requires approximate 27 percent lesser area than the original FIR filter.
Keywords :
CMOS integrated circuits; FIR filters; UHF filters; CMOS technology; SMIC; finite impulse response filter; fixed-point adder; frequency 1.3 GHz; high-performance 8-tap FIR filter; logarithmic number system; multiply-accumulate operations; power supply; size 0.13 mum; voltage 1.2 V; Adders; CMOS integrated circuits; Delay; Finite impulse response filter; Memory management; Pipelines; Read only memory;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Communications (ICC), 2011 IEEE International Conference on
Conference_Location :
Kyoto
ISSN :
1550-3607
Print_ISBN :
978-1-61284-232-5
Electronic_ISBN :
1550-3607
Type :
conf
DOI :
10.1109/icc.2011.5962827
Filename :
5962827
Link To Document :
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