DocumentCode :
2412324
Title :
Complexities of the non-volatile memory reliability testing caused by the test structure
Author :
Keshavarz, Abdol A. ; Spawn, Gregory S. ; Reyes, Nelson Delos ; Mincitar, Rogelio ; Dion, Laurent F.
Author_Institution :
Reliability & Process Control Dept., STMicroelectronics, Phoenix, AZ, USA
fYear :
2010
fDate :
17-21 Oct. 2010
Firstpage :
164
Lastpage :
167
Abstract :
This paper shows the sensitivity of the non-volatile memory reliability test to the test structure design and the pad sharing with other devices. Detailed results are presented to show how other devices on the same test structure can interfere with the EEPROM endurance test results and cause dramatic shifts in the data.
Keywords :
EPROM; integrated circuit reliability; integrated circuit testing; random-access storage; EEPROM endurance test; nonvolatile memory reliability testing; pad sharing; structure design; EPROM; Logic gates; Nonvolatile memory; Programming; Reliability; Threshold voltage; Transistors;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Integrated Reliability Workshop Final Report (IRW), 2010 IEEE International
Conference_Location :
Stanford Sierra, CA
ISSN :
1930-8841
Print_ISBN :
978-1-4244-8521-5
Type :
conf
DOI :
10.1109/IIRW.2010.5706515
Filename :
5706515
Link To Document :
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