DocumentCode :
2412521
Title :
Hierarchical global floorplacement using simulated annealing and network flow area migration
Author :
Choi, Wonjoon ; Bazargan, Kia
Author_Institution :
Dept. of Electr. & Comput. Eng., Minnesota Univ., Minneapolis, USA
fYear :
2003
fDate :
2003
Firstpage :
1104
Lastpage :
1105
Abstract :
Floorplanning large designs with many hard macros and IP blocks of various sizes is becoming an increasingly important and challenging problem. This paper presents a global floorplacement method that combines a hierarchical simulated annealing floorplanning method with a partitioning-based global placement technique. A novel area migration method, formulated as a min-cost, max-flow network flow problem, is used to improve area utilization, and provide a communication mechanism between the partitioning engine and the placement method for better design quality. The network flow area migration method can be used in managing incremental changes in the design as well. Our global placement wire length is 12% better than the detailed placement wire length of a previous work, while our global placement is almost 8 times faster than their global placement.
Keywords :
industrial property; integrated circuit layout; minimax techniques; simulated annealing; IP blocks; floorplanning; global placement wire length; hard macros; hierarchical global floorplacement; min-cost max-flow network flow problem; network flow area migration; partitioning engine; partitioning-based global placement technique; simulated annealing; Algorithm design and analysis; Circuit simulation; Design automation; Design methodology; Engines; Iterative methods; Routing; Scalability; Simulated annealing; Wire;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Design, Automation and Test in Europe Conference and Exhibition, 2003
ISSN :
1530-1591
Print_ISBN :
0-7695-1870-2
Type :
conf
DOI :
10.1109/DATE.2003.1253755
Filename :
1253755
Link To Document :
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