Title :
LIT - an automatic layout generation tool for trapezoidal association of transistors for basic analog building blocks
Author :
Girardi, Alesssandro ; Bampi, Sergio
Author_Institution :
Univ. Fed. do Rio Grande do Sul, Porto Alegre, Brazil
Abstract :
This paper describes a methodology for analog layout synthesis based on the automatic generation of an equivalent composite transistor with the same DC current characteristics of the transistors in the electrical schematic. The tool serves a dual purpose: i) the layout synthesis of analog blocks over a digital sea-of-gates prediffused array, and ii) the generation of custom associations of transistors for matched common-source input pairs and current mirrors. The LIT tool generates the layout in a line-matrix, sea-of-gates with gate isolation style of several blocks: the trapezoidal-like composite transistors and of matched transistor pairs. In addition, the tools provides an environment for manual analog cells placement and automatic routing. These features drastically reduce the design time, reduce costs and include matching properties.
Keywords :
analogue integrated circuits; circuit layout CAD; integrated circuit design; network routing; LIT automatic layout generation tool; analog building blocks; analog cells placement; analog layout synthesis methodology; automatic routing; current mirrors; digital sea-of-gates prediffused array; matched common-source input pairs; matched transistor pairs; trapezoidal association of transistors; trapezoidal-like composite transistors; Analog circuits; Character generation; Circuit synthesis; Circuit testing; Costs; DC generators; Fabrication; Field programmable gate arrays; Informatics; Routing;
Conference_Titel :
Design, Automation and Test in Europe Conference and Exhibition, 2003
Print_ISBN :
0-7695-1870-2
DOI :
10.1109/DATE.2003.1253756