• DocumentCode
    2412563
  • Title

    An application specific architecture for rate-distortion optimized motion compensation

  • Author

    Srinivas, P. ; Varadarajan, S. ; Kalapatapu, V. ; Bayoumi, M.

  • Author_Institution
    Center for Adv. Comput. Studies, Univ. of Southwestern Louisiana, Lafayette, LA, USA
  • fYear
    1993
  • fDate
    15-17 Dec 1993
  • Firstpage
    362
  • Lastpage
    369
  • Abstract
    The authors present the implementation details of the application specific architecture for rate-distortion optimized motion compensation. It is based on quadtree architecture which consists of two types of processors, P1 and P2. P1 processors are used at the leaf level and P2 processors are used at non-leaf levels. The proposed architecture supports pipelined operations both at the system level as well as at the processor level. The application specific prototype was designed for a block size of 4 × 4
  • Keywords
    computer architecture; application specific architecture; application specific prototype; leaf level; nonleaf level; pipelined operations; processor level; processors; quadtree architecture; rate-distortion optimized motion compensation; Application software; Computer architecture; Image coding; Motion compensation; Motion estimation; Partitioning algorithms; Prototypes; Pulse modulation; Rate-distortion; Video compression;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Computer Architectures for Machine Perception, 1993. Proceedings
  • Conference_Location
    New Orleans, LA
  • Print_ISBN
    0-8186-5420-1
  • Type

    conf

  • DOI
    10.1109/CAMP.1993.622492
  • Filename
    622492
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=2412563