DocumentCode :
2412654
Title :
An industrial/academic configurable system-on-chip project (CSoC): coarse-grain XPP-/Leon-based architecture integration
Author :
Becker, Jürgen ; Thomas, Alexander ; Vorbach, Martin ; Baumgarte, Volker
Author_Institution :
Inst. fuer Technik der Informationsverarbeitung, Karlsruhe Univ., Germany
fYear :
2003
fDate :
2003
Firstpage :
1120
Lastpage :
1121
Abstract :
Summary form only given. This paper describes the actual status and results of a dynamically Configurable System-on-Chip (CSoC) integration, consisting of a SPARC-compatible Leon processor-core, a commercial coarse-grain XPP-array of suitable size from PACT Informationstechnologie AG, and application-tailored global/local memory topology with efficient Amba-based communication interfaces. The given adaptive architecture is synthesized within an industrial/academic SoC project onto 0.18 and 0.13 μm UMC CMOS technologies at Universitaet Karlsruhe (TH). Due to exponential increasing CMOS mask costs, essential aspects for the industry are now adaptivity of SoCs, which can be realized by integrating reconfigurable re-usable hardware parts on different granularities into Configurable Systems-on-Chip (CSoCS).
Keywords :
CMOS integrated circuits; VLSI; integrated circuit design; system-on-chip; 0.13 micron; 0.18 micron; Amba-based communication interfaces; PACT XPP architecture; SPARC-compatible Leon processor-core; UMC CMOS technologies; adaptive architecture; application-tailored global/local memory topology; coarse-grain XPP-/Leon-based architecture integration; coarse-grain XPP-array; industrial/academic configurable SoC project; reconfigurable re-usable hardware parts; Europe; System testing; System-on-a-chip;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Design, Automation and Test in Europe Conference and Exhibition, 2003
ISSN :
1530-1591
Print_ISBN :
0-7695-1870-2
Type :
conf
DOI :
10.1109/DATE.2003.1253762
Filename :
1253762
Link To Document :
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