• DocumentCode
    2412789
  • Title

    Formal Validation of Hierarchical State Machines against Expectations

  • Author

    Toyn, Ian ; Galloway, Andy

  • Author_Institution
    Dept. of Comput. Sci., York Univ.
  • fYear
    2007
  • fDate
    10-13 April 2007
  • Firstpage
    181
  • Lastpage
    190
  • Abstract
    This paper explains some analyses that can be performed on a hierarchical finite state machine to validate that it performs as intended. Such a hierarchical state machine has transitions between states, triggered by conditions over inputs, with outputs determined per state in terms of inputs. Intentions are captured per state as expectations on input values. These expectations are expressed using the same condition language as transition triggers, extended to constrain rates of change as well as ranges. The analyses determine whether the expectations are consistent and whether the state machine conforms to the expectations. For the analyses to find no problems, the explicit expectations on the root state would be at least as strong as the implicit expectations of the state machine. One way of using the analyses is to reveal these implicit expectations. The analyses have been automated for statecharts built with the MathWorks´ Stateflow tool.
  • Keywords
    finite state machines; formal specification; hierarchical systems; mathematics computing; MathWorks Stateflow tool; formal validation; hierarchical finite state machines; statecharts; Australia; Automata; Automatic control; Computer science; Concrete; Concurrent computing; Connectors; Context modeling; Control system synthesis; Performance analysis;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Software Engineering Conference, 2007. ASWEC 2007. 18th Australian
  • Conference_Location
    Melbourne, Vic.
  • ISSN
    1530-0803
  • Print_ISBN
    0-7695-2778-7
  • Type

    conf

  • DOI
    10.1109/ASWEC.2007.23
  • Filename
    4159671