Title :
PARLAK: parametrized lock cache generator
Author :
Akgul, Bilge E S ; Mooney, Vincent J.
Author_Institution :
Sch. of Electr. & Comput. Eng., Georgia Inst. of Technol., Atlanta, GA, USA
Abstract :
A system-on-chip lock cache (SoCLC) is an intellectual property (IP) core that provides effective lock synchronization in a heterogeneous multiprocessor shared-memory system-on-a-chip (SoC). We present PARLAK, a parametrized lock cache generator tool. PARLAK generates a synthesizable SoCLC architecture with a user specified number of lock variables and user specified number and type(s) of processor(s). PARLAK can generate a full range of customized SoCLCs, from a version for two processors with 32 lock variables occupying 1,790 gates of area to a version for 14 processors with 256 lock variables occupying 37,380 gates of area (in TSMC 0.25μm technology). PARLAK is an important contribution to IP-generator tools for both custom and reconfigurable SoC designs.
Keywords :
cache storage; high level synthesis; industrial property; reconfigurable architectures; shared memory systems; synchronisation; system-on-chip; 0.25 micron; IP-generator tools; PARLAK; effective lock synchronization; heterogeneous multiprocessor shared-memory systems; intellectual property core; lock variables; parametrized lock cache generator; reconfigurable SoC designs; system-on-chip lock cache; Computer architecture; Costs; Digital signal processing; Hardware; Intellectual property; Libraries; Reconfigurable logic; Skeleton; Switches; System-on-a-chip;
Conference_Titel :
Design, Automation and Test in Europe Conference and Exhibition, 2003
Print_ISBN :
0-7695-1870-2
DOI :
10.1109/DATE.2003.1253771
