Selectively clocked CMOS logic style for low-power noise-immune operations in scaled technologies

Author

Sirisantana, Naran ; Roy, Kaushik

Author_Institution

Sch. of Electr. & Comput. Eng., Purdue Univ., West Lafayette, IN, USA

fYear

2003

fDate

2003

Firstpage

1160

Lastpage

1161

Abstract

This paper proposes a selectively clocked logic (SCL) style, based on skewed logic, for noise-tolerant low-power high-performance applications. Variations of the logic style, with multiple threshold voltage (MV_th-SCL) and multiple oxide thickness (Mt_ox-SCL) techniques, are also studied. Simulation results indicate that SCL, MV_th-SCL, and Mt_ox-SCL circuits reduce the total power consumption (leakage plus switching power) of the ISCAS benchmark circuits by 51.5%, 53.1%, and 69.6%, respectively, with over 25% improvement in noise immunity compared to Domino circuits with comparable performance.

Keywords

CMOS logic circuits; integrated circuit design; integrated circuit noise; logic circuits; low-power electronics; CMOS logic; Domino circuits; SCL style; high-performance applications; leakage power; low-power circuits; multiple oxide thickness; multiple threshold voltage; noise immunity; noise-immune circuits; noise-tolerant applications; power consumption reduction; scaled CMOS technologies; selectively clocked logic; skewed logic; switching power; CMOS logic circuits; CMOS technology; Circuit noise; Circuit topology; Clocks; Energy consumption; Latches; Logic circuits; Logic gates; Threshold voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Design, Automation and Test in Europe Conference and Exhibition, 2003

ISSN

1530-1591

Print_ISBN

0-7695-1870-2

Type

conf

DOI

10.1109/DATE.2003.1253781

Filename

1253781