DocumentCode
2413138
Title
Consequences of RAM bitline twisting for test coverage
Author
Schanstra, Ivo ; Van de Goor, Ad J.
Author_Institution
Infineon Technol. AG, Munich, Germany
fYear
2003
fDate
2003
Firstpage
1176
Lastpage
1177
Abstract
In order to reduce coupling effects between bitlines in static or dynamic RAMs bitline twisting can be used in the design. For testing, however, this has consequences for the to-be-used data backgrounds. A generic twisting scheme is introduced and the involved fault models are identified.
Keywords
DRAM chips; SRAM chips; fault diagnosis; integrated circuit testing; RAM bitline twisting; coupling effects; dynamic RAMs; fault models; generic twisting scheme; static RAMs; test coverage; to-be-used data backgrounds; DRAM chips; Design engineering; Europe; Fault diagnosis; Information technology; Logic; Random access memory; Read-write memory; Systems engineering and theory; Testing;
fLanguage
English
Publisher
ieee
Conference_Titel
Design, Automation and Test in Europe Conference and Exhibition, 2003
ISSN
1530-1591
Print_ISBN
0-7695-1870-2
Type
conf
DOI
10.1109/DATE.2003.1253788
Filename
1253788
Link To Document