FinFET performance advantage at 22nm: An AC perspective

Author

Guillorn, M. ; Chang, J. ; Bryant, A. ; Fuller, N. ; Dokumaci, O. ; Wang, X. ; Newbury, J. ; Babich, K. ; Ott, J. ; Haran, B. ; Yu, R. ; Lavoie, C. ; Klaus, D. ; Zhang, Y. ; Sikorski, E. ; Graham, W. ; To, B. ; Lofaro, M. ; Tornello, J. ; Koli, D. ; Yang,

Author_Institution

IBM Res., IBM T.J. Watson Res. Center, Yorktown Heights, NY

fYear

2008

fDate

17-19 June 2008

Firstpage

12

Lastpage

13

Abstract

At the 22 nm node, we estimate that superior electrostatics and reduced junction capacitance in FinFETs may provide a 13~23% reduction in delay relative to planar FETs. However, this benefit is offset by enhanced gate-to-source/drain capacitance (Cgs) in FinFETs. Here, we measure FinFET C_gs capacitance at 22 nm-like dimensions and determine that, with optimization, the FinFET capacitance penalty can be limited to <6%, resulting in an overall advantage of up to 17% over a planar technology.

Keywords

MOSFET; electrostatics; FinFET; electrostatics; enhanced gate-to-source/drain capacitance; junction capacitance; planar technology; size 22 nm; Analytical models; Delay estimation; Electrostatics; FETs; FinFETs; Hafnium; Parasitic capacitance; Silicides; Silicon on insulator technology; Space technology; FinFET; parasitic capacitance;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Technology, 2008 Symposium on

Conference_Location

Honolulu, HI

Print_ISBN

978-1-4244-1802-2

Electronic_ISBN

978-1-4244-1803-9

Type

conf

DOI

10.1109/VLSIT.2008.4588544

Filename

4588544