Asymmetrical transistor-clamped H-bridge cascaded multilevel inverter

This paper presents an asymmetrical cascaded multilevel inverter based on five-level transistor-clamped H-bridge power cell. Two-cell configuration with dc link voltage ratio of 4:1 is presented. The modulation method is based on the fundamental frequency switching. Analysis of the inverter output voltage and harmonics is presented. Injection of the third harmonics as to maximize the output voltage and the issue of the inverse power flow in the low voltage cell are presented. The prototype of the proposed inverter is built and the experimental results are obtained to verify its functionality.