Three-dimensional stress engineering in FinFETs for mobility/on-current enhancement and gate current reduction

Author

Saitoh, Masumi ; Kaneko, Akio ; Okano, Kimitoshi ; Kinoshita, Tomoko ; Inaba, Satoshi ; Toyoshima, Yoshiaki ; Uchida, Ken

Author_Institution

Corp. R&D Center, Toshiba Corp., Yokohama

fYear

2008

fDate

17-19 June 2008

Firstpage

18

Lastpage

19

Abstract

In this paper, the first systematic study of uniaxial stress effects on mobility (mu)/on-current (I_on) enhancement and gate current (I_g) reduction in FinFETs is described. We demonstrate for the first time that I_g of (110) side-surface pFinFETs is largely reduced by longitudinal compressive stress due to out-of-plane mass increase. (110) n/pFinFETs are superior to (100) FinFETs in terms of higher mu/I_on enhancement ratio by longitudinal strain and comparable/higher short-channel I_dsat. Three-dimensional stress design in FinFETs including transverse and vertical stresses is proposed based on the understanding of stress effects beyond bulk piezoresistance.

Keywords

MOSFET; compressive strength; electron mobility; piezoresistance; 3D stress engineering; FinFET; bulk piezoresistance; gate current reduction; longitudinal compressive stress; mobility/on-current enhancement; transverse stress; uniaxial stress effects; vertical stress; Capacitive sensors; Compressive stress; FETs; FinFETs; Large scale integration; Piezoresistance; Scattering; Strain measurement; Tensile strain; Tensile stress;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Technology, 2008 Symposium on

Conference_Location

Honolulu, HI

Print_ISBN

978-1-4244-1802-2

Electronic_ISBN

978-1-4244-1803-9

Type

conf

DOI

10.1109/VLSIT.2008.4588547

Filename

4588547