Analysis of Data Remanence in a 90nm FPGA

Author

Tuan, Tim ; Strader, Tom ; Trimberger, Steve

Author_Institution

Xilinx, San Jose

fYear

2007

fDate

16-19 Sept. 2007

Firstpage

93

Lastpage

96

Abstract

FPGAs are increasingly used in military applications, the security of a design when the part is powered off is an important property that needs to be analyzed. In this paper, we study data remanence in modern FPGAs using a custom 90nm FPGA designed for this test. The effects of temperatures, architecture, memory topology, and power off methods are analyzed. We find that different memory cells in the FPGA architecture have different remanence properties depending on their circuit design, data content, leakage and supply noise. To our knowledge, this is the first study of data remanence in FPGAs and in deep-submicron ICs.

Keywords

field programmable gate arrays; logic design; FPGA design; data content; data remanence; deep-submicron IC; design security; memory cells; memory topology; military applications; power off method; size 90 nm; supply noise; Circuit noise; Circuit synthesis; Circuit testing; Circuit topology; Data analysis; Data security; Field programmable gate arrays; Memory architecture; Remanence; Temperature;

fLanguage

English

Publisher

ieee

Conference_Titel

Custom Integrated Circuits Conference, 2007. CICC '07. IEEE

Conference_Location

San Jose, CA

Print_ISBN

978-1-4244-1623-3

Electronic_ISBN

978-1-4244-1623-3

Type

conf

DOI

10.1109/CICC.2007.4405689

Filename

4405689