Title :
Novel and cost-efficient single metallic silicide integration solution with dual Schottky-barrier achieved by aluminum inter-diffusion for FinFET CMOS technology with enhanced performance
Author :
Lee, Rinus Tek-Po ; Koh, Alvin Tian-Yi ; Fang, Wei-Wei ; Tan, Kian-Ming ; Lim, Andy Eu-Jin ; Liow, Tsung-Yang ; Shue-Yin, Chow ; Yong, Anna M. ; Wong, Hoong Shing ; Lo, Guo-Qiang ; Samudra, Ganesh S. ; Chi, Dong-Zhi ; Yeo, Yee-Chia
Author_Institution :
Dept. of Electr. & Comput. Eng., Nat. Univ. of Singapore, Singapore
Abstract :
We have developed a novel and cost-efficient silicide integration solution to achieve a hole barrier height of 215 meV and electron barrier height of 665 meV simultaneously with a single metallic silicide based on aluminum inter-diffusion. It is proposed that aluminum diffuses into PtSi and forms an alloy, which lowers the electron barrier height of PtSi due to a change in the intrinsic PtSi workfunction. Additionally, we have integrated platinum germanosilicide with an ultra-low hole barrier height of 215 meV in P-FinFETs to provide a 21% enhancement in drive current performance, which is attributed to the 20% reduction in series resistance. We have also ascertained the compatibility of PtSiGe with laser thermal annealing for further performance enhancement.
Keywords :
CMOS integrated circuits; Ge-Si alloys; MOSFET; Schottky barriers; platinum compounds; work function; FinFET CMOS technology; PtSiGe; aluminum inter-diffusion; dual Schottky-barrier; electron barrier; hole barrier; intrinsic workfunction; laser thermal annealing; metallic silicide integration; series resistance; Aluminum; Annealing; CMOS technology; Cost function; Degradation; Electrons; FinFETs; Platinum; Silicides; Temperature;
Conference_Titel :
VLSI Technology, 2008 Symposium on
Conference_Location :
Honolulu, HI
Print_ISBN :
978-1-4244-1802-2
Electronic_ISBN :
978-1-4244-1803-9
DOI :
10.1109/VLSIT.2008.4588551