Title :
Improved FET characteristics by laminate design optimization of metal gates - Guidelines for optimizing metal gate stack structure -
Author :
Kadoshima, M. ; Matsuki, T. ; Mise, N. ; Sato, M. ; Hayashi, M. ; Aminaka, T. ; Kurosawa, E. ; Kitajima, M. ; Miyazaki, S. ; Shiraishi, K. ; Chikyo, T. ; Yamada, K. ; Aoyama, T. ; Nara, Y. ; Ohji, Y.
Author_Institution :
Semicond. Leading Edge Technol., Inc. (Selete), Tsukuba
Abstract :
A laminate design technology of metal gates is proposed to improve FET characteristics regardless of EOT and gate dielectric material. The laminated metal gate structures are basically composed of low-Rs(sheet resistance) metal/ WF(work-function)-lowering layer/ WFM(WF determining metal). A thin WFM (~2 nm) laminated by the Si-based WF-lowering layer such as poly-Si or TaSiN brings an additional benefit of dramatic improvements in mobility and PBTI in nFETs. A thick WFM (~10 nm) suppresses the WF-lowering in pFETs. The concept of the laminate design is indispensable for improving the performance in CMOSFETs.
Keywords :
MOSFET; dielectric materials; CMOSFET; FET characteristics; gate dielectric material; laminate design optimization; laminate design technology; laminated metal gate structures; metal gate stack structure; CMOSFETs; Channel bank filters; Design optimization; Electrodes; FETs; Guidelines; High K dielectric materials; High-K gate dielectrics; Laminates; Tin;
Conference_Titel :
VLSI Technology, 2008 Symposium on
Conference_Location :
Honolulu, HI
Print_ISBN :
978-1-4244-1802-2
Electronic_ISBN :
978-1-4244-1803-9
DOI :
10.1109/VLSIT.2008.4588559
