DocumentCode
2413610
Title
Tutorial: synchronous dynamic memory test construction-a field approach
Author
Vollrath, Joerg
Author_Institution
White Oak Semicond., Sandston, VA, USA
fYear
2000
fDate
2000
Firstpage
59
Lastpage
64
Abstract
This paper gives an introduction how to construct dynamic memory tests and test flows. Step by step a basic march test is developed choosing a pattern, voltage levels and timings. Starting with this basic pattern, modifications for characterization, diagnostic and speed testing are discussed. These variations are then used to construct a test sequence to ensure functionality according to the data sheet specification
Keywords
integrated circuit testing; integrated memory circuits; basic pattern; march test; memory tests; synchronous dynamic memory test; test flows; test sequence; Analog circuits; Capacitors; Circuit testing; Logic circuits; Logic testing; SDRAM; Semiconductor device testing; Timing; Tutorial; Voltage;
fLanguage
English
Publisher
ieee
Conference_Titel
Memory Technology, Design and Testing, 2000. Records of the 2000 IEEE International Workshop on
Conference_Location
San Jose, CA
ISSN
1087-4852
Print_ISBN
0-7695-0689-5
Type
conf
DOI
10.1109/MTDT.2000.868616
Filename
868616
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