DocumentCode :
2413665
Title :
March tests for realistic faults in two-port memories
Author :
Hamdioui, Said ; Rodgers, Mike ; Van de Goor, Ad J. ; Eastwick, David
Author_Institution :
Delft Univ. of Technol., Netherlands
fYear :
2000
fDate :
2000
Firstpage :
73
Lastpage :
78
Abstract :
This paper starts with an overview of realistic faults models for two-port memories, divided into single-port faults and unique two-port faults. The latter faults can not be detected with the conventional single-port memory tests; they require special tests. Thereafter the paper presents a set of four march tests detecting the unique two-port faults. Three of the tests have a time complexity of θ(n) and one of θ (√n), whereby n is the size of the two-port memory cell array. Two of the four tests have been implemented at Intel and applied to 1500 two-port memories passing all single port tests. The test results show that two dies fail to pass the implemented tests, which means that the tests are superior
Keywords :
computational complexity; digital simulation; integrated circuit testing; memory architecture; realistic faults models; single-port faults; time complexity; two-port memories; Analytical models; Bridge circuits; Built-in self-test; Circuit faults; Circuit testing; Coupling circuits; Interference; Paper technology; Read-write memory; SPICE;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Memory Technology, Design and Testing, 2000. Records of the 2000 IEEE International Workshop on
Conference_Location :
San Jose, CA
ISSN :
1087-4852
Print_ISBN :
0-7695-0689-5
Type :
conf
DOI :
10.1109/MTDT.2000.868618
Filename :
868618
Link To Document :
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