Defect analysis and realistic fault model extensions for static random access memories

Resistive short defects were injected in the sense amplifier, memory cells and the address decoder of an SRAM memory. The behavior of these defects were examined using a transistor-level simulation framework. An unbalanced sense amplifier fault, consisting of a resistive short injected in the pull-down path of a sense amplifier, was examined. The scope of this type of fault could be broadened to cover any type of defect that makes the right and left side of the sense amplifier to become asymmetric. The effects of resistive shorts in the pull-up and pulldown path of a memory cell were examined. For the defects in the pull-up path, the effectiveness of different test methods designed to detect this type of defects were examined. The pause method is effective for resistive defects with large values while the weak write DfT method can detect small defects by introducing structural changes to the memory cell. In the case of a defect in the pull-down path of the memory cell, two consecutive read operations were determined to be the most effective solution to detect these defects. Three types of defects were injected in the dynamic logic address decoder. The defects affecting the pulldown and the input to the N-FETs manifested themselves as the address decoder selects more than one or zero memory cell. The defects affecting the restore unit and the word address line resulted in not selecting any cell in the memory. The injected defects in the restore unit could not be detected without the addition of DfT logic to the unit