Title :
A 24-parallel processing DS-UWB system
Author :
Kang, Kyu-Min ; Choi, Sang-Sung
Author_Institution :
Electron. & Telecommun. Res. Inst. (ETRI), Daejeon, South Korea
Abstract :
We present a hardware efficient 24-parallel processing architecture for the binary phase-shift keying (BPSK) direct sequence ultra-wideband (DS-UWB) system. A DS-UWB baseband modem is implemented and tested on the field programmable gate arrays (FPGAs) with a digital-to-analog (D/A) converter operating at the sampling rate of 1.32 GHz. Experimental results show that the DS-UWB prototype system delivers high definition (HD) content over a 5-m UWB channel with less than 1times10-9 bit error rate.
Keywords :
digital-analogue conversion; error statistics; field programmable gate arrays; parallel processing; phase shift keying; spread spectrum communication; ultra wideband communication; DS-UWB system; FPGA; baseband modem; binary phase shift keying; bit error rate; digital-to-analog converter; direct sequence ultra-wideband system; field programmable gate arrays; hardware efficient; parallel processing architecture; Baseband; Binary phase shift keying; Field programmable gate arrays; Hardware; Modems; Phase shift keying; Prototypes; Sampling methods; Testing; Ultra wideband technology; DS-UWB; RAKE receiver; correlator; parallel processing; pulse shaping FIR filter;
Conference_Titel :
Consumer Electronics, 2009. ISCE '09. IEEE 13th International Symposium on
Conference_Location :
Kyoto
Print_ISBN :
978-1-4244-2975-2
Electronic_ISBN :
978-1-4244-2976-9
DOI :
10.1109/ISCE.2009.5156870
