Scaling evaluation of BE-SONOS NAND flash beyond 20 nm

Author

Lue, Hang-Ting ; Tzu-Hsuan Hsu ; Lai, S.C. ; Hsiao, Y.H. ; Peng, W.C. ; Liao, C.W. ; Huang, Y.F. ; Hong, S.P. ; Wu, M.T. ; Hsu, Tzu-Hsuan ; Lien, N.Z. ; Wang, S.Y. ; Yang, L.W. ; Yang, T. ; Chen, K.C. ; Hsieh, K.Y. ; Liu, Rich ; Lu, Chih-Yuan

Author_Institution

Emerging Central Lab., Macronix Int. Co. Ltd., Hsinchu

fYear

2008

fDate

17-19 June 2008

Firstpage

116

Lastpage

117

Abstract

We have successfully fabricated and characterized sub-30 nm and sub-20 nm BE-SONOS NAND flash. Good device characteristics are achieved through two innovative processes: (1) a low-energy tilt-angle STI pocket implantation to suppress the STI corner edge effect, and (2) a drain offset using an additional oxide liner to improve the short-channel effect. The conventional self-boosting program-inhibit and ISPP (incremental step pulse programming) for MLC storage are demonstrated for 20 nm BE-SONOS NAND operation. Read current stability and read disturb life time are also evaluated. The estimated number of storage electrons is only 50-100, and for the first time we have demonstrated successful data retention after 150degC baking in the ldquofew-electronrdquo regime. Our results strongly suggest that BE-SONOS is a promising charge-trapping (CT) technology for NAND Flash scaling.

Keywords

NAND circuits; flash memories; BE-SONOS NAND flash; charge-trapping technology; data retention; drain offset; incremental step pulse programming; low-energy tilt-angle STI pocket implantation; short-channel effect; storage electrons; Capacitors; Degradation; Electrons; Etching; Lead compounds; Linear programming; Stability; Testing; Tunneling; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Technology, 2008 Symposium on

Conference_Location

Honolulu, HI

Print_ISBN

978-1-4244-1802-2

Electronic_ISBN

978-1-4244-1803-9

Type

conf

DOI

10.1109/VLSIT.2008.4588584

Filename

4588584