DocumentCode
2414162
Title
Channel-stress study on gate-size effects for damascene-Gate pMOSFETs with top-cut compressive stress liner and eSiGe
Author
Mayuzumi, S. ; Yamakawa, S. ; Kosemura, D. ; Takei, M. ; Wang, J. ; Ando, T. ; Tateshita, Y. ; Tsukamoto, M. ; Wakabayashi, H. ; Ohno, T. ; Ogura, A. ; Nagashima, N.
Author_Institution
Semicond. Bus. Group, SONY Corp., Atsugi
fYear
2008
fDate
17-19 June 2008
Firstpage
126
Lastpage
127
Abstract
Damascene gate process enhances the drivability in shorter gate length region, as compared to conventional gate 1st process for pFETs with compressive stress SiN liner and embedded SiGe. The origin of the gate length effect is investigated for the first time by using the UV-Raman spectroscopy. Moreover, the relationship between channel strain and gate width for damascene gate pFETs is analyzed and the effect is also demonstrated. It is found that channel strain is considerably enhanced in shorter gate length and narrower gate width by the combination of damascene gate process and stress enhancement techniques.
Keywords
Ge-Si alloys; MOSFET; Raman spectroscopy; ultraviolet spectroscopy; UV-Raman spectroscopy; compressive stress liner; damascene-gate; eSiGe; gate-size effects; pMOSFET; Analytical models; Capacitive sensors; Compressive stress; Germanium silicon alloys; High K dielectric materials; High-K gate dielectrics; MOSFETs; Silicon compounds; Silicon germanium; Spectroscopy;
fLanguage
English
Publisher
ieee
Conference_Titel
VLSI Technology, 2008 Symposium on
Conference_Location
Honolulu, HI
Print_ISBN
978-1-4244-1802-2
Electronic_ISBN
978-1-4244-1803-9
Type
conf
DOI
10.1109/VLSIT.2008.4588588
Filename
4588588
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