Author :
Auth, C. ; Cappellani, A. ; Chun, J.-S. ; Dalis, A. ; Davis, A. ; Ghani, T. ; Glass, G. ; Glassman, T. ; Harper, M. ; Hattendorf, M. ; Hentges, P. ; Jaloviar, S. ; Joshi, S. ; Klaus, J. ; Kuhn, K. ; Lavric, D. ; Lu, M. ; Mariappan, H. ; Mistry, K. ; Norri
Author_Institution :
Logic Technol. Dev., Intel Corp., Hillsboro, OR
Abstract :
Two key process features that are used to make 45 nm generation metal gate + high-k gate dielectric CMOS transistors are highlighted in this paper. The first feature is the integration of stress-enhancement techniques with the dual metal-gate + high-k transistors. The second feature is the extension of 193 nm dry lithography to the 45 nm technology node pitches. Use of these features has enabled industry-leading transistor performance and the first high volume 45 nm high-k + metal gate technology.
Keywords :
CMOS integrated circuits; MOSFET; high-k dielectric thin films; ultraviolet lithography; CMOS transistors; dry lithography; high-k gate dielectrics; high-k transistors; metal gate transistors; nanotechnology node pitches; size 45 nm; strain-enhanced transistors; stress-enhancement; wavelength 193 nm; Capacitive sensors; Compressive stress; Germanium silicon alloys; High K dielectric materials; High-K gate dielectrics; Inorganic materials; Lithography; MOS devices; Silicon germanium; Tensile stress;
