Author :
Kubicek, S. ; Schram, T. ; Rohr, E. ; Paraschiv, V. ; Vos, R. ; Demand, M. ; Adelmann, C. ; Witters, T. ; Nyns, L. ; Delabie, A. ; Ragnarsson, L-Å ; Chiarella, T. ; Kerner, C. ; Mercha, A. ; Parvais, B. ; Aoulaiche, M. ; Ortolland, C. ; Yu, H. ; Veloso, A
Abstract :
We discuss several advancements over our previous report (S. Kubicek, 2006): - Introduction of conventional stress boosters resulting in 16% and 11% for nMOS and pMOS respectively. For the first time the compatibility of SMT (stress memorization technique) with high-kappa/metal gate is demonstrated. In addition, we developed a blanket SMT process that does not require a photo to protect the pMOS by selecting a hydrogen-rich SiN film. - A comprehensive study of HfSiO and HfO2 as function of La/Al doping and spike/laser annealing. Parameters studied include Vt tuning, reliability and process control. - Demonstration of fast invertor delay of 10 ps including high frequency response analysis revealing the negative impact of high metal sheet resistance and parasitic metal-poly interface oxide.
Keywords :
CMOS integrated circuits; MOSFET; aluminium; frequency response; hafnium compounds; integrated circuit reliability; lanthanum; laser beam annealing; semiconductor doping; silicon compounds; Al; Al doping; CMOS transistor; HfO2; HfSiO; La; La doping; SiN; frequency response analysis; high-kappa gate; invertor delay; laser annealing; metal gate; metal sheet resistance; nMOS; pMOS; parasitic metal-poly interface oxide; process control; spike annealing; strain enhanced low-VT CMOS; stress boosters; stress memorization technique; time 10 ps; Annealing; Capacitive sensors; Doping; Hafnium oxide; Laser tuning; MOS devices; Protection; Silicon compounds; Stress; Surface-mount technology;
