A 0.22 nJ/b/iter 0.13 μm turbo decoder chip using inter-block permutation interleaver

This paper presents a high speed turbo decoder containing 32 MAP decoders with a inter-block permutation interleaver. The proposed butterfly network guarantees contention-free property and promises parallel processing of turbo decoder without performance degradation. In addition, our approach also features a relocated radix-2 x 2 ACS structure to reduce the critical path delay. After manufacturing by 0.13 μm CMOS process, the test results show the energy efficiency is 0.22 nJ/b/iter in the 160 Mb/s data rate.