Title :
Impact of tantalum composition in TaC/HfSiON gate stack on device performance of aggressively scaled CMOS devices with SMT and strained CESL
Author :
Goto, M. ; Tatsumura, K. ; Kawanaka, S. ; Nakajima, K. ; Ichihara, R. ; Yoshimizu, Y. ; Onoda, H. ; Nagatomo, K. ; Sasaki, T. ; Fukushima, T. ; Nomachi, A. ; Inumiya, S. ; Oguma, H. ; Miyashita, K. ; Harakawa, H. ; Inaba, S. ; Ishida, T. ; Azuma, A. ; Aoy
Author_Institution :
Center for Semicond. R&D, Toshiba Corp., Yokohama
Abstract :
We report TaCx/HfSiON gate stack CMOS device with simplified gate 1st process from the viewpoints of fixed charge generation and its impact on the device performance. Moderate Metal Gate / High-K dielectric (MG/HK) interface reaction is found to be a dominant factor to improve device performance. By optimizing TaCx composition, fixed charge free TaCx/HfSiON device is successfully fabricated. Also, we have demonstrated that the strain effect in deeply scaled devices can be enhanced by eliminating the fixed charges in HfSiON, for the first time. Utilizing Stress Memorization Technique (SMT) and strained Contact Etch Stop Layer (CESL), Lg = 35 nm high performance TaCx/HfSiON devices is achieved.
Keywords :
CMOS integrated circuits; etching; hafnium compounds; high-k dielectric thin films; stress effects; tantalum compounds; CMOS devices; SMT; TaC/HfSiON gate stack; device performance; fixed charge generation; metal gate/high-K dielectric interface reaction; strain effect; strained CESL; strained contact etch stop layer; stress memorization technique; tantalum composition; Atherosclerosis; CMOS process; Capacitive sensors; Composite materials; Degradation; Dielectric devices; Dielectric materials; Large scale integration; Research and development; Surface-mount technology;
Conference_Titel :
VLSI Technology, 2008 Symposium on
Conference_Location :
Honolulu, HI
Print_ISBN :
978-1-4244-1802-2
Electronic_ISBN :
978-1-4244-1803-9
DOI :
10.1109/VLSIT.2008.4588591
