A 1-V, 1.4-2.5 GHz Charge-Pump-Less PLL for a Phase Interpolator Based CDR

Author

Park, Jaejin ; Liu, Jenlung Frank ; Carley, L. Richard ; Yue, C. Patrick

Author_Institution

California Univ., Santa Barbara

fYear

2007

fDate

16-19 Sept. 2007

Firstpage

281

Lastpage

284

Abstract

A 1.4-2.5 GHz charge-pump-less phase locked loop (PLL) and a linear phase interpolator (PI) with dummy cells to enhance linearity are implemented in 0.13-mum CMOS. The loop filter with RC integrators and a V-I converter are proposed for achieving wide frequency range and high linearity in the voltage controlled oscillator (VCO) under a low supply voltage. The measured RMS and peak-peak jitters are 4.05 ps and 28.18 ps at 2 GHz, respectively. The measured DNL and INL of the PI are 0.27 LSB and 0.68 LSB, respectively.

Keywords

CMOS integrated circuits; convertors; phase locked loops; voltage-controlled oscillators; CMOS; RC integrator; V-I converter; charge-pump-less phase locked loop; frequency 1.4 GHz to 2.5 GHz; frequency 2 GHz; linear phase interpolator; size 0.13 mum; time 28.18 ps; time 4.05 ps; voltage controlled oscillator; Charge pumps; Circuits; Frequency conversion; Linearity; Low pass filters; Low voltage; Phase locked loops; Rail to rail outputs; Switches; Voltage-controlled oscillators;

fLanguage

English

Publisher

ieee

Conference_Titel

Custom Integrated Circuits Conference, 2007. CICC '07. IEEE

Conference_Location

San Jose, CA

Print_ISBN

978-1-4244-1623-3

Electronic_ISBN

978-1-4244-1623-3

Type

conf

DOI

10.1109/CICC.2007.4405733

Filename

4405733