• DocumentCode
    2414334
  • Title

    A 14-b 30MS/s 0.75mm2 Pipelined ADC with On-Chip Digital Self-Calibration

  • Author

    Lee, Ho-Young ; Oh, Tae-Hwan ; Park, Ho-Jin ; Lee, Hae-Seung ; Spaeth, Mark ; Kim, Jae-Whui

  • Author_Institution
    Samsung Electron. Co., Yongin
  • fYear
    2007
  • fDate
    16-19 Sept. 2007
  • Firstpage
    313
  • Lastpage
    316
  • Abstract
    A 14-b 30 MS/s CMOS pipelined ADC is presented. To facilitate digital calibration, a simple 1-b per stage architecture with redundancy is used. The ADC fully integrates digital self-calibration, which performs overall sequence by one flag signal. Implemented in a 90 nm digital CMOS process, the prototype ADC achieves 83.7 dB SFDR and 69.3 dB SNDR with calibration. Its active area is 0.75 mm2 including the on-chip calibration logic and the total power consumes 106 mW with 3.3 V and 1.0 V supply.
  • Keywords
    CMOS integrated circuits; analogue-digital conversion; pipeline processing; digital CMOS process; onchip digital self-calibration; pipelined ADC; power 106 mW; size 90 nm; voltage 1 V; voltage 3.3 V; CMOS digital integrated circuits; CMOS process; CMOS technology; Calibration; Energy consumption; Error correction; Logic; MIM capacitors; Redundancy; USA Councils;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Custom Integrated Circuits Conference, 2007. CICC '07. IEEE
  • Conference_Location
    San Jose, CA
  • Print_ISBN
    978-1-4244-1623-3
  • Electronic_ISBN
    978-1-4244-1623-3
  • Type

    conf

  • DOI
    10.1109/CICC.2007.4405741
  • Filename
    4405741
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=2414334