DocumentCode
2414406
Title
A Time-Interleaved Track & hold in 0.13 μm CMOS sub-sampling a 4 GHz signal with 43 dB SNDR
Author
Louwsma, Simon M. ; Van Tuijl, Ed J M ; Vertregt, Maarten ; Nauta, Bram
Author_Institution
Twente Univ., Enschede
fYear
2007
fDate
16-19 Sept. 2007
Firstpage
329
Lastpage
332
Abstract
A 16-channel time-interleaved track and hold is presented. Three techniques are introduced enabling a high bandwidth and linearity and good timing alignment. Integrated ADCs are used to evaluate the performance of the T/H. Single channel performance is 43 dB SNDR at an input frequency of 4 GHz. Multi-channel performance is 48 dB SNDR at 1.35 GS/s with an ERBW of 1 GHz. The power consumption of the T/H including clock-driver and buffers is 74 mW.
Keywords
CMOS integrated circuits; analogue-digital conversion; signal sampling; CMOS subsampling; ERBW; SNDR; frequency 1 GHz; frequency 4 GHz; integrated ADC; power 74 mW; size 0.13 μm; time-interleaved track and hold; Bandwidth; Capacitance; Capacitors; Circuits; Clocks; Energy consumption; Frequency; Linearity; Switches; Voltage;
fLanguage
English
Publisher
ieee
Conference_Titel
Custom Integrated Circuits Conference, 2007. CICC '07. IEEE
Conference_Location
San Jose, CA
Print_ISBN
978-1-4244-0786-6
Electronic_ISBN
978-1-4244-1623-3
Type
conf
DOI
10.1109/CICC.2007.4405745
Filename
4405745
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