A Sample-Time Error Compensation Technique for Time-Interleaved ADC Systems

Sample-time error among different channels of a time-interleaved analog-to-digital converter (ADC) is a factor in significant degradation of the ADC performance, especially in high frequencies. A two-channel, time-interleaved ADC structure with a background sample-time error compensation technique has been implemented. The sample-time error detection technique uses random data and has been implemented in the digital domain at a low level of complexity. The error correction is performed by adjusting the delay of the clock path of one channel, using a 6-bit digitally-controlled delay element (DCDE). At a sampling rate of 400 MSamples/s, the experimental results show that the spurious-free dynamic range (SFDR) of the ADC system is improved to 58.8 dB at 190 MHz. The ADC system achieves a signal-to-noise-and-distortion ratio (SNDR) of 59.6 dB at 5 MHz and 55.2 dB at 190 MHz after compensation. This error compensation method is especially suitable for time-interleaved ADCs used in digital data communication systems.