Author :
Zhibin Ren ; Pei, G. ; Li, J. ; Yang, B.F. ; Takalkar, R. ; Chan, K. ; Xia, G. ; Zhu, Z. ; Madan, A. ; Pinto, T. ; Adam, Tijjani ; Miller, Jason ; Dube, A. ; Black, L. ; Weijtmans, J.W. ; Yang, B. ; Harley, E. ; Chakravarti, A. ; Kanarsky, T. ; Pal, R. ;
Abstract :
We report a successful implementation of epitaxially grown Phosphorus-doped (P-doped) embedded SiC stressors into SOI nMOSFETs. We identify a process integration scheme that best preserves the SiC strain and minimizes parasitic resistance. At a substitutional C concentration (Csub) of ~1.0%, high performance nFETs with SiC stressors demonstrate ~9% enhanced Ieff and ~15% improved Idlin against the well calibrated control devices. It is found that the tensile liner technique provides further performance improvement for nFETs with SiC stressors, whereas the stress memory technique (SMT) does not provide performance gain in a laser annealing process that is used to preserve SiC strain. The material quality of the SiC stressors strongly affects strain transfer.
Keywords :
MOSFET; laser beam annealing; silicon compounds; system-on-chip; wide band gap semiconductors; SOI nMOSFET; SiC; control device calibration; embedded phosphorus implementation; laser annealing process; nFETs; parasitic resistance; process integration scheme; strain transfer; stress memory technique; tensile liner technique; Implants; Logic gates; Materials; Resistance; Silicon; Silicon carbide; Strain;
