Title :
An All-Digital 90-Degree Phase-Shift DLL with Loop-Embedded DCC for 1.6Gbps DDR Interface
Author :
Bae, Jun-Hyun ; Seo, Jin-Ho ; Yeo, Hwan-Seok ; Kim, Jae-Whui ; Sim, Jae-Yoon ; Park, Hong-June
Author_Institution :
POSTECH, Pohang
Abstract :
An all-digital 90deg phase-shift DLL is proposed for 1.6 Gbps DDR interface by using a loop-embedded DCC and a binary phase detector with the lock range extended to 0~4pi radians. The DCC has a small delay and the fixed rising-edge property for loop-embedding. The chip fabricated with a 0.13 um CMOS process gives the DLL data rate of 667 Mbps~1.6 Gbps and the output duty cycle of 47.8%~49% for the input duty cycle of 23%~76%, at 1.6 Gbps and 1.2 V.
Keywords :
CMOS digital integrated circuits; delay lock loops; phase detectors; CMOS process; DLL; all-digital 90-degree phase-shift delayed lock loop; binary phase detector; bit rate 1.6 Gbit/s; high-speed double-data rate interface; loop-embedded duty cycle corrector circuit; size 0.13 mum; voltage 1.2 V; CMOS process; Clocks; Counting circuits; Delay effects; Delay lines; Gas detectors; Phase detection; Signal generators; Tellurium;
Conference_Titel :
Custom Integrated Circuits Conference, 2007. CICC '07. IEEE
Conference_Location :
San Jose, CA
Print_ISBN :
978-1-4244-1623-3
Electronic_ISBN :
978-1-4244-1623-3
DOI :
10.1109/CICC.2007.4405755
