Reliability Trends with Advanced CMOS Scaling and The Implications for Design

Scaling (for enhanced performance, increased functionality and cost reduction reasons) has pushed existing CMOS materials much closer to their intrinsic reliability limits. This will require that designers pay very close attention to both front-end-of-line (FEOL) and back-end-of-line (BEOL) reliability issues. As for the FEOL reliability issues, hyper-thin gate oxide leakage, time-dependent dielectric breakdown (TDDB), and negative-bias temperature instability (NBTI) are near the top the list. In the case of hyper-thin gate oxides, TDDB can manifest itself in terms of multiple soft-breakdown events thus causing an unwanted rise in leakage; NBTI-induced p-channel device degradation tends to have a significant impact on minimum-voltage circuit operation. As for the important BEOL reliability issues, the top ones are: electromigration (EM), stress migration (SM), low-k dielectric TDDB, and mechanical weaknesses associated with the low-k films and their interfaces. The EM associated with Cu interconnects will continue to worsen with scaling due to increased interface effects; SM will require even fewer vacancies to coalesce which can cause an unwanted via resistance rise; and relatively poor low-k TDDB behavior and low-k mechanical-weakness issues may require special interconnect layout considerations.