Title :
A NOVEL JAVA COPROCESSOR with data hazard handling on FPGA for IC bank card
Author :
Yonghong Bai ; Liji Wu ; Beibei Wang ; Xiangmin Zhang
Author_Institution :
Nat. Lab. for Inf. Sci. & Technol., Tsinghua Univ., Beijing, China
Abstract :
A design of Java coprocessor used in IC bank card is presented in this paper. A 4Kb true dual port SRAM is used for stack to reduce data hazard. Two stack top registers keep same data with the top of stack, which can build a bypass that can handle the data hazard of pipeline. This Java coprocessor can execute 88 Java card instructions, with a size of 8185 gates at a clock of 125MHz.
Keywords :
Java; SRAM chips; clocks; coprocessors; field programmable gate arrays; smart cards; FPGA; IC bank card; Java card instructions; Java coprocessor; clocks; data hazard handling; data hazard reduction; gate size; stack top registers; true-dual-port SRAM; Abstracts; Clocks; Frequency estimation; Frequency synthesizers; Java; Pipelines; Random access memory;
Conference_Titel :
Solid-State and Integrated Circuit Technology (ICSICT), 2014 12th IEEE International Conference on
Conference_Location :
Guilin
Print_ISBN :
978-1-4799-3296-2
DOI :
10.1109/ICSICT.2014.7021163
