A Reconfigurable Implementation of the New Secure Hash Algorithm

The main applications of the hash functions are met in the fields of communication´s integrity and signature authentication. Many hash algorithms have been investigated and developed in the last years. This work is related to hash functions FPGA implementation. Field programmable gate arrays (FPGAs) being reconfigurable, flexible and physically secure are a natural choice for implementation of hash functions in a broad range of applications with different area-performance requirements. We propose a configurable secure hash algorithm (SHA) processor for extended signature authentication. This paper investigates different optimizations algorithms of recent techniques that have been proposed in the literature. In our implementation based on Xilinx Virtex FPGAs, the throughput of SHA processor is equal to 1296 Mbit/s. Speed/area results from these processors are analyzed and shown to compare favorably with other FPGA-based implementations. A fastest data throughput is achieved by our optimized algorithm