A Synthesis-based Bandwidth Enhancing Technique for CML Buffers/Amplifiers

Author

Pi, Deyi ; Chun, Byung-Kwan ; Heydari, Payam

Author_Institution

California Univ., Irvine

fYear

2007

fDate

16-19 Sept. 2007

Firstpage

467

Lastpage

470

Abstract

A synthesis-based bandwidth enhancing technique for current-mode-logic (CML) buffers/amplifiers is presented, which achieves bandwidth-enhancement-ratio (BWER) of 4.84, close to a proven theoretical upper limit of 4.93. By employing a complete step-by-step design methodology, the proposed technique can be applied to any load condition, which is characterized by the ratio between the load capacitance and the output capacitance of the transconductor cell. Several prototype buffer/amplifier circuits are designed using lower order passive networks to save chip area. The test chip is fabricated in a 0.18 mum CMOS process, and measurements show a BWER of 3.8.

Keywords

CMOS digital integrated circuits; buffer circuits; current-mode logic; network synthesis; wideband amplifiers; CML buffers/amplifier; CMOS process; current-mode-logic buffers/amplifier; size 0.18 mum; synthesis-based bandwidth enhancing technique; Bandwidth; CMOS logic circuits; CMOS technology; Capacitance; Circuit synthesis; Design methodology; Network synthesis; Passive networks; Prototypes; Transconductors;

fLanguage

English

Publisher

ieee

Conference_Titel

Custom Integrated Circuits Conference, 2007. CICC '07. IEEE

Conference_Location

San Jose, CA

Print_ISBN

978-1-4244-1623-3

Electronic_ISBN

978-1-4244-1623-3

Type

conf

DOI

10.1109/CICC.2007.4405775

Filename

4405775