DocumentCode
2415418
Title
Analysis of 2D operators on topographic and non-topographic processor architectures
Author
Zarándy, Ákos ; Rekeczky, Csaba ; Földesy, Péter
Author_Institution
MTA-SZTAKI Budapest, Budapest
fYear
2008
fDate
14-16 July 2008
Firstpage
57
Lastpage
62
Abstract
2D operators were categorized based on their implementation methods on different low-power topographic and non-topographic single-chip processor architectures. The implementation methods of the 2D operators in the individual categories are shown, and their processor utilization efficiency is analyzed. The execution times of the basic operators on the different architectures are calculated, the power efficiency figures and the frame-rate versus resolution chart are derived.
Keywords
cellular neural nets; parallel architectures; 2D operators; nontopographic processor architectures; processor utilization efficiency; topographic processor architectures; Cellular neural networks; Charge coupled devices; Computer architecture; Libraries; Parallel architectures; Shape; Skeleton; Testing; Xenon;
fLanguage
English
Publisher
ieee
Conference_Titel
Cellular Neural Networks and Their Applications, 2008. CNNA 2008. 11th International Workshop on
Conference_Location
Santiago de Compostela
Print_ISBN
978-1-4244-2089-6
Electronic_ISBN
978-1-4244-2090-2
Type
conf
DOI
10.1109/CNNA.2008.4588650
Filename
4588650
Link To Document