• DocumentCode
    2415468
  • Title

    A 0.8-1.2GHz Single-Phase Resonant-Clocked FIR Filter with Level-Sensitive Latches

  • Author

    Sathe, Visvesh S. ; Kao, Jerry C. ; Papaefthymiou, Marios C.

  • Author_Institution
    Michigan Univ., Ann Arbor
  • fYear
    2007
  • fDate
    16-19 Sept. 2007
  • Firstpage
    583
  • Lastpage
    586
  • Abstract
    In this paper, we present the design and experimental validation of RF1, a 0.8-1.2GHz frequency-scalable, resonant-clocked FIR filter test-chip with level-sensitive latches. Designed using a fully automated ASIC flow, RF1 was fabricated in a 0.13mum CMOS process with an on-chip inductor and clock generator. At its resonant frequency of 1.03GHz, RF1 dissipates 132mW, with clock power accounting for only 10.8% of total power dissipation. Resonating 42pF of clock load, RF1 achieves 76% clock-power efficiency over CV2 f.
  • Keywords
    CMOS integrated circuits; FIR filters; UHF filters; UHF integrated circuits; application specific integrated circuits; ASIC flow; CMOS process; clock generator; frequency 0.8 GHz to 1.2 GHz; level-sensitive latches; on-chip inductor; power 132 mW; resonant-clocked FIR filter; size 0.13 mum; Application specific integrated circuits; CMOS logic circuits; Clocks; Degradation; Finite impulse response filter; Flip-flops; Latches; Resonance; Resonant frequency; Timing;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Custom Integrated Circuits Conference, 2007. CICC '07. IEEE
  • Conference_Location
    San Jose, CA
  • Print_ISBN
    978-1-4244-1623-3
  • Electronic_ISBN
    978-1-4244-1623-3
  • Type

    conf

  • DOI
    10.1109/CICC.2007.4405799
  • Filename
    4405799