A 5.4 GHZ All-Digital Phase-Locked Loop with a wide output swing and high-linearity DAC

Author

Li Liu ; Weixin Gai

Author_Institution

Inst. of Microelectron., Peking Univ., Beijing, China

fYear

2014

fDate

28-31 Oct. 2014

Firstpage

1

Lastpage

3

Abstract

A 5.4 GHz All-Digital Phase-Locked Loop (ADPLL) is presented in this paper. The ADPLL is designed in 65nm CMOS process. A 7 bit wide output swing and high linearity digital-to-analog converter (DAC) is used in this ADPLL to achieve good jitter performance. The proposed current-mode DAC with dual compensation circuits compensates the channel modulation effect. It demonstrates output swing of 1 V and DNL of 0.1 LSB. The frequency resolution of the DCO is 52 kHz. The rms jitter of the ADPLL is 0.53 ps.

Keywords

CMOS digital integrated circuits; digital phase locked loops; digital-analogue conversion; jitter; ADPLL; CMOS process; DCO; DNL; all-digital phase-locked loop; channel modulation effect; current-mode DAC; digital-to-analog converter; digitally controlled oscillator; dual compensation circuit; frequency 5.4 GHz; frequency 52 kHz; frequency resolution; high-linearity DAC; jitter performance; size 65 nm; voltage 1 V; voltage output swing; Capacitors; Frequency modulation; Jitter; Linearity; Tuning;

fLanguage

English

Publisher

ieee

Conference_Titel

Solid-State and Integrated Circuit Technology (ICSICT), 2014 12th IEEE International Conference on

Conference_Location

Guilin

Print_ISBN

978-1-4799-3296-2

Type

conf

DOI

10.1109/ICSICT.2014.7021199

Filename

7021199