Title :
1.1 TMACS/mW Load-Balanced Resonant Charge-Recycling Array Processor
Author :
Karakiewicz, Rafal ; Genov, Roman ; Cauwenberghs, Gert
Author_Institution :
Toronto Univ., Toronto
Abstract :
A resonant adiabatic mixed-signal 128 times 256 array processor achieves 1.1 TMACS (1012 multiply-accumulates per second) per mW of power from a 1.6 V DC supply. The 1.9 mum times 9 mum 3T NMOS unit cell with single-wire pitch multiplexed bit/compute line provides charge-conserving lb-lb multiplication and single-wire analog accumulation. A stochastic data modulation scheme minimizes on-chip capacitance variability maintaining clock oscillations near resonance.
Keywords :
CMOS logic circuits; adders; microprocessor chips; mixed analogue-digital integrated circuits; modulation; multiplying circuits; stochastic processes; 3T NMOS; charge-conserving multiplication; load-balanced resonant charge-recycling array processor; resonant adiabatic mixed-signal array processor; single-wire analog accumulation; single-wire pitch multiplexed bit/compute line; size 1.9 mum; size 9 mum; stochastic data modulation scheme; voltage 1.6 V; Capacitance; Clocks; Concurrent computing; Encoding; Energy dissipation; Energy efficiency; RLC circuits; Random access memory; Stochastic resonance; Voltage;
Conference_Titel :
Custom Integrated Circuits Conference, 2007. CICC '07. IEEE
Conference_Location :
San Jose, CA
Print_ISBN :
978-1-4244-1623-3
Electronic_ISBN :
978-1-4244-1623-3
DOI :
10.1109/CICC.2007.4405804
