DocumentCode
2415916
Title
SIMD array on FPGA for B/W image processing
Author
Nieto, A. ; Brea, V.M. ; Vilariño, D.L.
Author_Institution
Dept. of Electron. & Comput. Sci., Univ. of Santiago de Compostela, Santiago de Compostela
fYear
2008
fDate
14-16 July 2008
Firstpage
202
Lastpage
207
Abstract
This paper introduces a topographic implementation of an SIMD array for B/W image processing of 48 times 48 processing elements on an FPGA. The computation is done with Boolean and shift operators. The connectivity among processing elements is set through the classical NEWS system. The array provides the functionality of a CNNUM. The paper shows examples of algorithms and applications, and it also examines possible upscalings of the 48 times 48 array on larger FPGAs.
Keywords
field programmable gate arrays; image processing; parallel processing; BW image processing; Boolean operator; FPGA; SIMD array; Application software; Arithmetic; Cellular neural networks; Clocks; Computer science; Field programmable gate arrays; Image processing; Logic arrays; Microcomputers; Read-write memory;
fLanguage
English
Publisher
ieee
Conference_Titel
Cellular Neural Networks and Their Applications, 2008. CNNA 2008. 11th International Workshop on
Conference_Location
Santiago de Compostela
Print_ISBN
978-1-4244-2089-6
Electronic_ISBN
978-1-4244-2090-2
Type
conf
DOI
10.1109/CNNA.2008.4588678
Filename
4588678
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