Title :
Reliability in CMOS VLSI circuits
Author :
Kukkal, Pankaj ; Bowles, John
Author_Institution :
Dept. of Electr. & Comput. Eng., South Carolina Univ., Columbia, SC, USA
Abstract :
This paper presents some of the most important reliability techniques, and considerations associated with combinational CMOS VLSI circuits. The authors discuss reliability with regards to fault tolerance and testability. Topics discussed include common fault models, simulation of faults at the gate and layout level, test vector generation, redundancy techniques. and design-for-testability for combinational VLSI circuits
Keywords :
CMOS integrated circuits; VLSI; circuit reliability; combinatorial circuits; fault location; integrated circuit testing; integrated logic circuits; logic design; logic testing; redundancy; CMOS VLSI circuits; combinational VLSI circuits; common fault models; design-for-testability; fault tolerance; gate level faults; layout level fault simulation; redundancy; test vector generation; testability; Circuit faults; Circuit simulation; Circuit testing; Design for testability; Fault tolerance; Fault tolerant systems; Graphics; Integrated circuit reliability; Logic circuits; Very large scale integration;
Conference_Titel :
System Theory, 1991. Proceedings., Twenty-Third Southeastern Symposium on
Conference_Location :
Columbia, SC
Print_ISBN :
0-8186-2190-7
DOI :
10.1109/SSST.1991.138558
