DocumentCode
2416126
Title
Compact Fault Recovering Flip-Flop with Adjusting Clock Timing Triggered by Error Detection
Author
Yasuda, Shin´ichi ; Fujita, Shinobu
Author_Institution
Corp. R&D Center, Kawasaki
fYear
2007
fDate
16-19 Sept. 2007
Firstpage
721
Lastpage
724
Abstract
We propose novel compact fault recovering flip-flops (CFR-FFs) which can recover timing error and soft error caused by process variation, supply voltage fluctuation, attacking high energy particle, and so on. Those FFs are composed of an error detector and a clock controller, which re-raises a clock to latch correct data upon error detecting. We propose two kinds of CFR-FFs. One is that the clock rises every cycle, and the other is that the clock rises only when data has changed. These FFs were fabricated by a 0.25 mum CMOS process. Error rates were measured by applying a noise signal to the supply voltage. While the error rate was over 46 % for a conventional FF, it was 1.4 % and 2.2 % for each CFR-FF with only 1.41 and 1.65 times area overhead, respectively.
Keywords
CMOS integrated circuits; clocks; error detection; fault diagnosis; flip-flops; synchronisation; CMOS process; clock controller; clock timing; compact fault recovering flip-flop; error detection; fault recovery; size 0.25 mum; soft error recovery; timing error recovery; CMOS process; Clocks; Detectors; Error analysis; Error correction; Fault detection; Flip-flops; Noise measurement; Timing; Voltage fluctuations;
fLanguage
English
Publisher
ieee
Conference_Titel
Custom Integrated Circuits Conference, 2007. CICC '07. IEEE
Conference_Location
San Jose, CA
Print_ISBN
978-1-4244-1623-3
Electronic_ISBN
978-1-4244-1623-3
Type
conf
DOI
10.1109/CICC.2007.4405832
Filename
4405832
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