Title :
A 2GHz, 7W (max) 64b PowerTM Microprocessor Core
Author :
Murray, D. ; Burnette, J. ; Campbell, B. ; Chung, M. ; Fernandes, B. ; Ghosh, S. ; Goel, R. ; Hess, G. ; Hang Huang ; Zhibin Huang ; Javarappa, N. ; Kanapathipillai, P. ; Klass, F. ; Fang Liu ; Mehta, A. ; Modukuru, Y. ; Nerurkar, N. ; Radhakrishnan, A. ;
Author_Institution :
PA Semi, Inc., Santa Clara
Abstract :
The PA6T core is an out-of-order superscalar implementation of the power architecture. Power efficiency is achieved through micro-architecture, logic, and circuit optimizations. The processor is fabricated in a 65 nm, triple Vt, dual oxide 8 M CMOS process. Worst-case power dissipation at 2 GHz is 7 W.
Keywords :
CMOS integrated circuits; UHF integrated circuits; circuit optimisation; microprocessor chips; PA6T core; Power microprocessor core; circuit optimizations; frequency 2 GHz; out-of-order superscalar implementation; power 7 W; power architecture; word length 64 bit; CMOS logic circuits; CMOS process; Clocks; Energy consumption; Java; Logic circuits; Microprocessors; Out of order; Power dissipation; Testing;
Conference_Titel :
Custom Integrated Circuits Conference, 2007. CICC '07. IEEE
Conference_Location :
San Jose, CA
Print_ISBN :
978-1-4244-0786-6
DOI :
10.1109/CICC.2007.4405833
