Title :
Power-Efficient Dual-Supply 64kB L1 Caches in a 65nm CMOS Technology
Author :
Campbell, Brian ; Burnette, James ; Javarappa, Naveen ; Von Kaenel, Vincent
Author_Institution :
P.A. Semi Inc., Santa Clara
Abstract :
The 64 kB LI caches on the PA6T-1682M SoC CPU are composed of common data and tag structures fabricated in a 65 nm CMOS process and deliver a 1.5 cycle read latency with 32 GB/s bandwidth at 2 GHz. Several features optimize cache performance and power including power-down safe level shifters, streamlined dual-supply bitslices, fine-grain clock gating, and a centralized tag floorplan.
Keywords :
CMOS integrated circuits; cache storage; clocks; system-on-chip; 64 kB L1 caches; CMOS technology; CPU; SoC; bandwidth 2 GHz; bit rate 32 Gbit/s; centralized tag floorplan; fine grain clock gating; power down safe level shifters; power efficient; size 65 nm; streamlined dual supply bitslices; Bandwidth; CMOS process; CMOS technology; Central Processing Unit; Circuits; Clocks; Decoding; Logic arrays; Random access memory; Voltage;
Conference_Titel :
Custom Integrated Circuits Conference, 2007. CICC '07. IEEE
Conference_Location :
San Jose, CA
Print_ISBN :
978-1-4244-1623-3
Electronic_ISBN :
978-1-4244-1623-3
DOI :
10.1109/CICC.2007.4405834
