• DocumentCode
    2416228
  • Title

    A new memory monitoring scheme for memory-aware scheduling and partitioning

  • Author

    Suh, G. Edward ; Devadas, Srinivas ; Rudolph, Larry

  • Author_Institution
    Lab. for Comput. Sci., MIT, Cambridge, MA, USA
  • fYear
    2002
  • fDate
    2-6 Feb. 2002
  • Firstpage
    117
  • Lastpage
    128
  • Abstract
    We propose a low overhead, online memory monitoring scheme utilizing a set of novel hardware counters. The counters indicate the marginal gain in cache hits as the size of the cache is increased, which gives the cache miss-rate as a function of cache size. Using the counters, we describe a scheme that enables an accurate estimate of the isolated miss-rates of each process as a function of cache size under the standard LRU replacement policy. This information can be used to schedule jobs or to partition the cache to minimize the overall miss-rate. The data collected by the monitors can also be used by an analytical model of cache and memory behavior to produce a more accurate overall miss-rate for the collection of processes sharing a cache in both time and space. This overall miss-rate can be used to improve scheduling and partitioning schemes.
  • Keywords
    cache storage; monitoring; real-time systems; scheduling; storage management; LRU replacement policy; cache hits; cache miss-rate; cache size; marginal-gain counters; memory monitoring; memory-aware scheduling; partitioning; Analytical models; Computer architecture; Computer science; Computerized monitoring; Counting circuits; Hardware; Laboratories; Processor scheduling; Runtime; Yarn;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    High-Performance Computer Architecture, 2002. Proceedings. Eighth International Symposium on
  • ISSN
    1530-0897
  • Print_ISBN
    0-7695-1525-8
  • Type

    conf

  • DOI
    10.1109/HPCA.2002.995703
  • Filename
    995703