Title :
Design challenges of high speed ADC in CMOS technology for next generation optical communication applications
Author :
Long Zhao ; Yuhua Cheng
Author_Institution :
Shanghai Res. Inst. of Microelectron., Peking Univ., Shanghai, China
Abstract :
The next generation commercial optical communication requires ADCs with more than 50GS/s and at least 5 ENOB. For this ultra-high speed requirement, the time-interleaved architecture is the best choice among various types of ADCs. This paper first examines the key challenges of these high-speed time-interleaved ADCs from the perspective of designers. Then detailed design considerations are presented, including time-interleaved architecture, sub-ADC and the analysis of channel mismatch effects. Finally, digitally calibration designs are briefly introduced.
Keywords :
CMOS integrated circuits; analogue-digital conversion; high-speed integrated circuits; next generation networks; optical communication; CMOS technology; ENOB; analog-to-digital converters; channel mismatch effect analysis; digitally calibration designs; next generation commercial optical communication applications; subADC; time-interleaved ADC architecture; ultrahigh speed requirement; Abstracts; Integrated optics; MATLAB; Next generation networking; Optical design; Very large scale integration;
Conference_Titel :
Solid-State and Integrated Circuit Technology (ICSICT), 2014 12th IEEE International Conference on
Conference_Location :
Guilin
Print_ISBN :
978-1-4799-3296-2
DOI :
10.1109/ICSICT.2014.7021238
